1 – The EZPU architecture and technical choices

The architecture we will use for this project is an attempt to strike a balance between simplicity, visual presentation, and features. First and foremost, we want to provide a simple model for understanding the data-flow in processors. We want to put this model in the spotlight, and build the rest of the processor around that.

A very generalized model of processor data flow: The data lies in memory. Some of it is moved to the registers. From there, the data can be transformed, the results being written back into the registers. Finally, the modified data can be moved back to memory.

Secondly, we need to decide our feature set. We want our CPU to support a decently wide set of capabilities:

  • Addressable registers.
  • Control flow.
  • A stack.
  • Immediate values.
  • Enough memory to store programs, data segments, and a stack.

Keeping the basic model in mind, I put together an architecture that can support these features.

Data-path model of the EZPU architecture. The clock and other signals aren’t drawn here.

This model has the memory, registers, and transform module (ALU) in focus, similarly to the earlier simplified model. The rest of the modules sit above, to clearly separate them as assisting components.

An advantage of this model is that most instructions can be performed in only two sub-instructions, while the complex instructions take at most four. The data-flow of every instruction can be clearly traced through the data-paths, without having to keep track of many steps.

A disadvantage is that 4 multiplexers are needed to implement this (two of these are in the register file). To build an 8-bit multiplexer with 4 inputs, you need 4 chips, and it can get a little messy to build on breadboards.

We can easily add input and output to the model later if we so wish, by connecting a new module to bus A or B.

Almost all components will be primarily built out of the TTL chips of the 74LS series. These are readily available and have relatively high output current, meaning that we don’t have to worry about driving LEDs and multiple other chips at the same time. They also run on 5V, which we can supply from a typical phone charger for now. A reference manual for these chips can be found here.

I will explain each part of the processor as we build it. The next post will take a slight detour to talk about computers and data in general. After that we move on to the registers or ALU.

0 – Processor on a breadboard

An 8-bit register (74LS377) holding the binary value 01010101.

To many people, the inner workings of computers might as well be magic. Even if you know coding, there is no clear picture of how code is actually executed by the machine.

On this blog, we will try to shed some light on the inner workings of computers as we build an 8-bit processor on top of breadboards. The goal of the project will be to make a visually descriptive processor, while delving into elements of processors in various levels of detail on this blog.

The processor will use a homemade architecture dubbed ‘EZPU’, which features:

  • Directed data-paths
  • 4 addressable registers
  • 256 bytes of RAM
  • A stack pointer
  • Simple I/O

The exact architecture will be discussed in an upcoming post.

This is not the first project of its type, nor will it be the last. It is inspired by a video series by Ben Eater, where he builds the SAP-1 processor from the book “Digital Computer Electronics” by Albert P. Malvino. The ‘gimmick’ that differentiates the EZPU from others is a focus on data visualization, as well as a relative similarity in instruction sets to basic 86 processors. It is designed to be a teaching tool as a finished product, where processors like the SAP are designed to teach the one who builds it.

The topic of the next post is the EZPU architecture and a general overview of what a processor is.